The present disclosure relates to semiconductor devices and to methods of fabricating semiconductor devices.
A multigate transistor has been suggested as a scaling technology for increasing the density of semiconductor devices. Generally, a multigate transistor is characterized by a silicon body in the shape of a fin or nanowire being formed on a substrate, and a gate then being formed on a surface of the silicon body.
The multigate transistor allows for relatively easing scaling, as it employs a three-dimensional channel. Further, current control capability can be enhanced without with need for increased gate length of the multigate transistor. Furthermore, it is possible to effectively suppress a short channel effect (SCE) in which the electric potential of the channel region is influenced by the drain voltage.